1. Field of the invention
The present invention relates to a semiconductor device and a method of manufacturing the same, more particularly to a semiconductor device comprising a trench element separation structure and a method of manufacturing the same.
2. Description of the Related Art
Hitherto, a LOCOS (Local Oxidation of Silicon) method has been used for forming an element separation region of a semiconductor device; however, for the purpose of producing a highly integrated semiconductor device, a method including a trench dug in a semiconductor substrate for filling an insulation film therein has also been used as a candidate method that replaces the LOCOS method, which needs a wide extent in the transverse direction. However, when the trench is buried with a material such as a silicon oxide film similar to an interlayer insulation film, it is necessary to ensure a sufficient margin, as described below, for mask alignment of a diffusion layer and a contact portion, and this has been an obstacle to improving the degree of integration.
A prior art in which a trench is dug in the semiconductor substrate to embed an insulation film therein (hereinafter this art will be referred to as a first prior art example) will be described with reference to FIG. 1A and FIG. 1B. FIG. 1A is a sectional view of an insulated gate field effect transistor (hereinafter referred to as a MOS transistor) having a trench element separation structure of the first prior art example.
As shown in FIG. 1A, element separation trench 102 for element separation use is formed in silicon substrate 101, and then the trench is filled with a SiO2 film according to a chemical vapor deposition (CVD) method to form filling insulation film 103. Then in accordance with a manufacturing process of a normal MOS transistor, gate insulation film 104, gate electrode 105, source/drain region 106, 106a and interlayer insulation film 107 comprising a SiO2 made by a CVD method are formed on the silicon substrate.
Next, contact hole 108 for connecting the wiring is formed in source/drain region 106a, and contact plug 109 is filled in the contact hole 108. Subsequently, wiring 110 laid on interlayer insulation film 107 and contact plug 109 are connected.
In case of forming this contact hole 108, it is usual to provide a design margin X of a fixed value between contact hole 108 and element separation trench 102 giving consideration to mask alignment leeway between source/drain region 106a and contact hole 108. If the margin X is insufficient and positional misalignment of the mask takes place, as shown in FIG. 1B, contact hole 108a is formed partially overlapping with element separation trench 102. At the time when the contact hole is formed, etching time is usually set with a 30 to 100% margin over an expected normal time considering the influence of the dispersion of data such as the film thickness of interlayer insulation film 107 or the etching speed which is to be generated during a manufacturing process. If filling insulation film 103 filling element separation trench 102 and interlayer insulation film 107 are formed with the same material and the value of the margin X is insufficient, contact hole 108a formed by etching will dig filled insulation film 103.
In such a state, contact plug 109 filled in contact hole 108a will come to be connected with silicon substrate 101 at an exposed side wall of element separation trench 102. This contact plug 109 also connects with source/drain region 106a. Since silicon substrate 101 and source/drain region 106a are short-circuited as described above, the MOS transistor will fail to operate normally. A MOS transistor of FIG. 1B comprises gate insulation film 104, gate electrode 105 and source/drain regions 106, 106a in the same manner as that of FIG. 1A.
An invention developed for overcoming this kind of drawback is disclosed in Japanese Patent Laid-open Gazette 190847/1987 (hereinafter this art is referred to as a second prior art example). FIG. 2 is a sectional view of a MOS transistor having a trench element separation structure of the second prior art example.
On the surface of element separation trench 202 formed in silicon substrate 201, there is formed silicon nitride film 203 of several tens of nm in thickness, and the remaining part inside the trench is filled with filling insulation film 204. On the surface of silicon substrate 201 where no element separation structure is formed, gate insulation film 205, gate electrode 206 and source/drain region 207, 207a of the MOS transistor are formed, and interlayer insulation film 208 composed of an oxide film is formed thereon covering all the silicon substrate 201.
In the manufacturing process of the second prior art example, when contact hole 209 for connecting wiring is formed in source/drain region 207a and then wiring 211 laid on the interlayer insulation film is connected with source/drain region 207a of the MOS transistor under the condition that the mask alignment margin between source/drain region 207a and contact hole 209 is insufficient, it is probable that the contact hole will be formed partially overlapping with the element separation region. However, even in such a case, a silicon substrate on the side wall of element separation trench 202 is protected by silicon nitride film 203 because the etching speed of silicon nitride film 203 is slow compared with that of a silicon oxide film which constitutes interlayer insulation film 208. Consequently, there is no probability of a short circuit occurring between wiring 211 and silicon substrate 201.
Certainly, the second prior art example can solve the technical problem of the first prior art example. However, there is another problem in the technique of the second prior art example in that, since silicon nitride film 203 is directly deposited on the surface of a silicon substrate inside element separation trench 202 formed in silicon substrate 201, a crystal defect is generated in an area near the silicon substrate surface facing element separation trench 202 which is caused by thermal changes produced in the following processes, thereby causing an increase in the leak current which flows from a diffusion layer that constitutes source/drain region 207a to silicon substrate 201.
This is because the elastic strength of silicon nitride film 203 is remarkably large compared with that of the silicon oxide film, and hence when thermal changes are applied to silicon nitride film 203 after being deposited on the silicon substrate, thermal stress is produced within the silicon, thereby causing crystal defects.
Leak current of this kind carried from the diffusion layer to the silicon substrate functions not only to increase dissipation power during the operation waiting time of the semiconductor device, but to induce a latch-up phenomenon in the semiconductor device of a CMOS structure, thereby becoming a large cause of deteriorating the reliability of the product.
An object of the present invention is to provide a semiconductor device having a trench element separation structure and adapted to a high degree of integration while solving the technical problems of the prior art without having crystal defects produced in the silicon substrate, and a method of manufacturing the same.
Therefore, the semiconductor device of the present invention has a trench element separation region in a fixed region of the semiconductor substrate, the inside wall of the trench is covered with a first insulation film, and a second insulation film and a third insulation film are stacked in layers in this order and filled on the first insulation film in the trench.
Here, the third insulation film is formed so that the surface thereof may be positioned lower than the surface of the semiconductor substrate.
Further, an interlayer insulation film is formed so that it may cover the third insulation film and the semiconductor substrate, the interlayer insulation film is composed of a silicon oxide film and the third insulation film is composed of one of a silicon oxynitride film or a silicon nitride film, a silicon oxide film including excess silicon.
The semiconductor device according to another aspect of the present invention has a trench element separation region in a prescribed region of the semiconductor substrate of one conduction type, the inside wall of the trench is covered with the first insulation film, the second insulation film is filled on the first insulation film, and a diffusion layer of reverse conduction type is formed on the semiconductor substrate on the side wall of the upper region which constitutes an opening portion of the trench.
Here, a side wall insulation film is formed on the side wall of the opening portion of the aforementioned trench.
Now, a method of manufacturing the semiconductor device of the present invention comprises the steps of forming a trench on one main surface of the semiconductor substrate, thermally oxidizing an inside wall of said trench, filling the inside of said trench with a filling insulation film composed mainly of a silicon dioxide, etching back the filling insulation film to a level lower than the main surface of said semiconductor substrate, and filling the opening portion of said trench with a cap insulation layer composed mainly of a silicon nitride.
Here, the step of filling the opening portion of said trench with the cap insulation layer composed mainly of a silicon nitride comprises the steps of forming the insulation film composed mainly of a silicon nitride by attaching the insulation film so as to cover the opening portion of said trench, forming a resist pattern arranged to mask the opening portion of said trench, applying anisotropic etching to said insulation film using said resist pattern as a mask, removing said resist pattern, and removing a remained part of said insulation film positioned higher than the surface of said semiconductor substrate by a chemical polishing method.
A method of manufacturing the semiconductor device according to another aspect of the present invention comprises the steps of forming a trench in one main surface of the semiconductor substrate of one conduction type, thermally oxidizing the inside wall of the trench, filling the inside of the trench with the filling insulation film composed mainly of a silicon dioxide, etching back the filling insulation film to a level lower than the main surface of the semiconductor substrate, and forming the diffusion layer of a reverse conduction type on the exposed part of the main surface of the semiconductor substrate and the exposed part of the trench side wall.
A method of manufacturing the semiconductor device according to still another aspect of the present invention comprises the steps of forming a trench in one main surface of the semiconductor substrate of one conduction type, thermally oxidizing the inside wall of the trench, filling the inside of the trench with the filling insulation film composed mainly of a silicon dioxide, depositing an interlayer insulation film in such a manner that it covers the filling insulation film and thereafter forming a contact hole which penetrates the interlayer insulation film, and ion implanting impurities of a reverse conduction type through said contact hole into one main surface of the semiconductor substrate and the semiconductor substrate on the side wall of the trench both exposed by forming said contact hole.
Here, it is preferable to perform the ion implantation of impurities of the reverse conduction type by a rotational oblique ion implantation method.
In the semiconductor device of the present invention, the cap insulation layer formed in the opening portion of the trench prevents the filling insulation film from being etched at the time of forming the contact hole.
In the semiconductor device according to another aspect of the present invention, even when the filling insulation film is etched and a side wall of the trench is exposed at the time when the contact hole is formed, since the diffusion layer is formed on the exposed region of the semiconductor substrate, the conductive material filled in the contact hole and the semiconductor substrate do not contact with each other even if the contact hole is formed partially overlapping with the trench.
Further, since the insulation film of small thermal stress is embedded in the greater part of the inside of the trench which constitutes the trench element separation region, the thermal stress of the semiconductor substrate becomes small and hence the emergence of the crystal defect is considerably controlled.
The above and other object, features, and advantages of the present invention will become apparent from the following description based on the accompanying drawings which illustrate an example of a preferred embodiment of the present invention.